As electronic devices get smaller, the components within these devices must get smaller as well. Because of this, there has been an increased demand for the miniaturization of components and greater packaging density. Integrated Circuit (IC) package density is primarily limited by the area available for die mounting and the height of the package. One way of increasing the density is to stack multiple die or packages vertically in an IC package. Stacking multiple die or packages will maximize function and efficiency of the semiconductor package.
One method of stacking multiple die in an IC package is to use a folded over flexible substrate. In this method, a die and the other die are placed side by side on a flexible substrate. The flexible substrate is then folded over and the portion where the other die is placed covers the entire top surface of the die. In the case of more than two dies, the method is the same.
The above method is the current way of producing IC packages having multiple stacked die using a flexible substrate. However, there are several problems associated with using flexible substrates for producing IC packages having multiple stacked die. One problem is cost. Two metal layer flexible substrate tape is very expensive to use making certain packages cost prohibitive to the end user/client. Second, under current methods, connect density between dies is dramatically lower using a folded over substrate.
In order to provide high quality multi-chip stacked devices, the devices used for stacking must be either high yield FAB (i.e., memory devices) or known good die (KGD). Certain devices like ASIC and logic devices have a lower yield than devices like memory. Thus, these types of devices need to be screened if they are to be used in a multi-chip stacked device. A problem arises in that it is expensive to get a KGD prepared. Wafer component testing and burn-in testing is a very expensive process. However, testing of these types of devices is necessary in order to sort out potentially problematic chips and to prevent any quality and reliability issues.
Presently, there is a problem over the lack of known good die application into die stacking. If a logic or ASIC device is rejected after testing, the stack die coupled to these devices must be scraped. This is problematic to many end customers due to the cost of scraping good die which is stacked to a fail logic or ASIC device.
Therefore, a need existed to provide a device and method to overcome the above problems.